In embedded clock systems, the clock signal is embedded in the data signal so that it must be recovered from the data signal by a clock data recovery (CDR) circuit. To recover the clock signal, the CDR circuit uses, for example, a phase-locked loop so that an edge-locked clock signal is aligned with the data transition edges in the data signal. The edge-locked clock signal may also be denoted as a quadrature clock signal. Due to the edge alignment, the edge-locked clock signal is unsuitable for sampling the data signal. To properly sample the data signal, the CDR circuit also aligns an in-phase clock signal to be in quadrature (delayed by 90 degrees) with the edge-locked clock signal. In such systems, the receiver includes a phase detector that detects the phase between the clock signal and the data. A loop filter filters the phase detector output to produce a filtered phase difference so that the clock signal may be interpolated according to the filtered phase difference. The clock signal interpolation keeps the in-phase clock signal centered in the data eye so that the data may be sampled accordingly. The in-phase clock signal may also be denoted as the data sampling clock signal or the data clock signal.
For high-speed operation, the CDR circuit recovers the clock signal from equalized data as equalized by a decision feedback equalizer (DFE). Without such equalization, inter-symbol interference limits the achievable data rate. A simplified view of a conventional DFE 100 is shown in FIG. 1. A transmitted data signal (TX) drives a channel 101 over which a receiver including DFE 100 receives the data. The non-ideal properties of channel 101 cause the inter-symbol interference that is addressed by DFE 100. The data clock signal as recovered by the CDR circuit (not illustrated) clocks a slicer 110 to sample the incoming data. As known in the communication arts, slicer 110 (which may also be designated as a signal slicer or a bit slicer) includes a comparator that compares the incoming data to a threshold value to output the data samples. The sampled data from slicer 110 enters a delay chain represented by register 115 in DFE 100. The delay chain is also clocked by the data clock signal. The data samples of the received data signal in the delay chain are each given an associated weight as represented by a gain stage 120 before the sum of the weighted samples from the delay chain are subtracted from the received data signal at an adder 105. The combination of the delay chain and the gain thus forms a feedback finite impulse response (FIR) filter. Although this operation is conventional, note that adder 105 is implemented in the analog domain since the received data prior to the sampling by slicer 110 is not rail-to-rail. The different gains applied by gain stage 120 in response to changes in the properties of channel 101 then introduce a varying delay to the received data after passing through adder 105 due to its analog operation. After operation of slicer 110, this delay is unknown to the CDR circuit since the CDR circuit processes the post-adder received data signal. The edge-locked clock signal is thus skewed with regard to the actual data transitions. The received data should be sampled in quadrature to the data edges but the offset between the perceived data transitions and the actual data transitions causes the in-phase sampling to be too delayed in phase such that at higher data rates the sampling is not properly positioned within the data eye. This improper sampling leads to errors in recovering the data.
Accordingly, there is a need in the art for improved sampling of received data that has been equalized by a decision feedback equalizer.